Wakeup Time From Low-Power Mode; External Clock Source Characteristics; Table 33. Low-Power Mode Wakeup Timings; Table 34. High-Speed External User Clock Characteristics - STMicroelectronics STM32F042F4 Manual

Electrical characteristics
6.3.6

Wakeup time from low-power mode

The wakeup times given in
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in
Symbol Parameter
Wakeup from Stop
t
WUSTOP
mode
Wakeup from
t
WUSTANDBY
Standby mode
Wakeup from Sleep
t
WUSLEEP
mode
6.3.7

External clock source characteristics

High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in
the recommended clock input waveform is shown in
source AC timing
Symbol
f
HSE_ext
V
HSEH
V
HSEL
t
w(HSEH)
t
w(HSEL)
t
r(HSE)
t
f(HSE)
60/117
Table 33

Table 33. Low-power mode wakeup timings

Conditions
Regulator in run
mode
Regulator in low
power mode
-
-
diagram.

Table 34. High-speed external user clock characteristics

Parameter
User external clock source frequency
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
OSC_IN high or low time
OSC_IN rise or fall time
DocID025832 Rev 5
are the latency between the event and the execution of
Table 21: General operating
Typ @V
= 2.0 V = 2.4 V = 2.7 V
3.2 3.1
7.0 5.8
60.4 55.6
4 SYSCLK cycles
Figure 15: High-speed external clock
(1)
Min
-
0.7 V
DDIOx
V
SS
15
-
STM32F042x4 STM32F042x6
conditions..
V
DD = DDA
= 3 V = 3.3 V
2.9 2.9 2.8
5.2 4.9 4.6
53.5 52 51
6.3.14. However,
Section
Typ Max
8 32
- V
DDIOx
- 0.3 V
DDIOx
- -
- 20
Max Unit
5
9
µs
-
-
Unit
MHz
V
ns