Electrical characteristics
6.3.6
Wakeup time from low-power mode
The wakeup times given in
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop or Standby mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
The wakeup source from Standby mode is the WKUP1 pin (PA0).
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in
Symbol
Parameter
Wakeup from Stop
t
WUSTOP
mode
Wakeup from
t
WUSTANDBY
Standby mode
Wakeup from Sleep
t
WUSLEEP
mode
62/117
Table 33
are the latency between the event and the execution of
Table 21: General operating
Table 33. Low-power mode wakeup timings
Conditions
Regulator in run
mode
Regulator in low
power mode
DocID025832 Rev 2
Typ @V
DD =
= 2.0 V = 2.4 V = 2.7 V
3.2
3.1
2.9
7.0
5.8
5.2
60.4
55.6
53.5
4 SYSCLK cycles
STM32F042xx
conditions.
V
DDA
Max Unit
= 3 V
= 3.3 V
2.9
2.8
5
4.9
4.6
9
52
51
-
-
μs
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