Electrical characteristics
6.3.5
Wakeup time from low-power mode
The wakeup times given in
the first user instruction. The device goes in low-power mode after the WFE (Wait For
Event) instruction, in the case of a WFI (Wait For Interruption) instruction, 16 CPU cycles
must be added to the following timings due to the interrupt latency in the Cortex M0
architecture.
The SYSCLK clock source setting is kept unchanged after wakeup from Sleep mode.
During wakeup from Stop mode, SYSCLK takes the default setting: HSI 8 MHz.
The wakeup source from Sleep and Stop mode is an EXTI line configured in event mode.
All timings are derived from tests performed under the ambient temperature and supply
voltage conditions summarized in
Symbol
t
Wakeup from Stop mode
WUSTOP
t
Wakeup from Sleep mode
WUSLEEP
6.3.6
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.
The external clock signal has to respect the I/O characteristics in
the recommended clock input waveform is shown in
source AC timing
Symbol
f
HSE_ext
V
HSEH
V
HSEL
t
w(HSEH)
t
w(HSEL)
t
r(HSE)
t
f(HSE)
1. Guaranteed by design, not tested in production.
52/102
Table 28
Table 28. Low-power mode wakeup timings
Parameter
diagram.
Table 29. High-speed external user clock characteristics
Parameter
User external clock source frequency
OSC_IN input pin high level voltage
OSC_IN input pin low level voltage
OSC_IN high or low time
OSC_IN rise or fall time
DocID026079 Rev 3
are the latency between the event and the execution of
Table 18: General operating
Figure 13: High-speed external clock
(1)
Min
-
0.7 V
DDIOx
V
SS
15
-
STM32F038x6
conditions..
Typ @ V
DDA
Max
= 1.8 V
= 3.3 V
3.5
2.8
5.3
4 SYSCLK cycles
-
Section
6.3.13. However,
Typ
Max
8
32
-
V
DDIOx
-
0.3 V
DDIOx
-
-
-
20
Unit
µs
µs
Unit
MHz
V
ns
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