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Enhanced Serial Audio Interface (ESAI, ESAI_1, ESAI_2, ESAI_3)
9.1.4
Serial Transmit 3/Receive 2 Data Pin (SDO3/SDI2)
SDO3/SDI2 is used as the SDO3 signal for transmitting data from the TX3 serial transmit shift register
when programmed as a transmitter pin, or as the SDI2 signal for receiving serial data to the RX2 serial
receive shift register when programmed as a receiver pin. SDO3/SDI2 is an input when data is being
received by the RX2 shift register. SDO3/SDI2 is an output when data is being transmitted from the TX3
shift register. In the on-demand mode with an internally generated bit clock, the SDO3/SDI2 pin becomes
high impedance for a full clock period after the last data bit has been transmitted, assuming another data
word does not follow immediately. If a data word follows immediately, there is no high-impedance
interval.
SDO3/SDI2 may be programmed as a general-purpose I/O pin (PC8) when the ESAI SDO3 and SDI2
functions are not being used.
9.1.5
Serial Transmit 4/Receive 1 Data Pin (SDO4/SDI1)
SDO4/SDI1 is used as the SDO4 signal for transmitting data from the TX4 serial transmit shift register
when programmed as transmitter pin, or as the SDI1 signal for receiving serial data to the RX1 serial
receive shift register when programmed as a receiver pin. SDO4/SDI1 is an input when data is being
received by the RX1 shift register. SDO4/SDI1 is an output when data is being transmitted from the TX4
shift register. In the on-demand mode with an internally generated bit clock, the SDO4/SDI1 pin becomes
high impedance for a full clock period after the last data bit has been transmitted, assuming another data
word does not follow immediately. If a data word follows immediately, there is no high-impedance
interval.
SDO4/SDI1 may be programmed as a general-purpose I/O pin (PC7) when the ESAI SDO4 and SDI1
functions are not being used.
9.1.6
Serial Transmit 5/Receive 0 Data Pin (SDO5/SDI0)
SDO5/SDI0 is used as the SDO5 signal for transmitting data from the TX5 serial transmit shift register
when programmed as transmitter pin, or as the SDI0 signal for receiving serial data to the RX0 serial shift
register when programmed as a receiver pin. SDO5/SDI0 is an input when data is being received by the
RX0 shift register. SDO5/SDI0 is an output when data is being transmitted from the TX5 shift register. In
the on-demand mode with an internally generated bit clock, the SDO5/SDI0 pin becomes high impedance
for a full clock period after the last data bit has been transmitted, assuming another data word does not
follow immediately. If a data word follows immediately, there is no high-impedance interval.
SDO5/SDI0 may be programmed as a general-purpose I/O pin (PC6) when the ESAI SDO5 and SDI0
functions are not being used
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
9-4
Freescale Semiconductor
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