Quad Instruction Execution - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

DSP Architecture
The TigerSHARC processor has four general-purpose external interrupts,
. The processor also has internally generated interrupts for the two
IRQ3-0
timers, DMA channels, link ports, arithmetic exceptions, multiprocessor
vector interrupts, and user-defined software interrupts. Interrupts can be
nested through instruction commands. Interrupts have a short latency and
do not abort currently executing instructions. Interrupts vector directly to
a user-supplied address in the interrupt table register file, removing the
overhead of a second branch.
The branch penalty in a deeply pipelined processor such as the Tiger-
SHARC processor can be compensated for by the use of a branch target
buffer (BTB) and branch prediction. The branch target address is stored
in the BTB. When the address of a jump instruction, which is predicted
by the user to be taken in most cases, is recognized (the tag address), the
corresponding jump address is read from the BTB and is used as the jump
address on the next cycle. Thus the latency of a jump is reduced from
three to six wasted cycles to zero wasted cycles. If this address is not stored
in the BTB, the instruction must be fetched from memory.
Other instructions also use the BTB to speed up these types of branches.
These instructions are interrupt return, call return, and computed jump
instructions.
Immediate extensions are associated with IALU or sequencer (control
flow) instructions. These instructions are not specified by the program-
mer, but are implied by the size of the immediate data used in the
instructions.
For more information on the sequencer, BTB, and immediate extensions,
see "Sequencer Register Groups" on page 2-15.

Quad Instruction Execution

The TigerSHARC processor can execute up to four instructions per cycle
from a single memory block, due to the 128-bit wide access per cycle. The
ability to execute several instructions in a single cycle derives from a Static
1-14 ADSP-TS101 TigerSHARC Processor
Hardware Reference