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SFD Register Bit Maps
BIPOLAR SUPPLY FAIL DETECT (BSn SFD) REGISTERS
Table 5. Register 0xA0, 0xA8 BSnOVTH
(Power-On Default 0xFF)
Bit
Name
R/W
7–0
OV7–OV0
R/W
Table 6. Register 0xA1, 0xA9 BSnOVHYST
(Power-On Default 0x00)
Bit
Name
R/W
7–5
Reserved
N/A
4–0
HY4–HY0
R/W
Table 9. Register 0xA4, 0xAC BSnSEL (Power-On Default 0x00)
Bit
Name
R/W
7
POL
R/W
6−4
GF2−GF0
R/W
3
Reserved
N/A
2
RSEL
R/W
1−0
FS1−FS0
R/W
Description
8-Bit Digital Value for OV
Threshold on BSn SFD
Description
Cannot Be Used
5-Bit Digital Value for Hysteresis
on OV Threshold of BSn SFD
Description
Polarity of Bipolar
POL
SFDn
0
1
GF2
GF1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
Cannot Be Used
Note: When POL is set to 1 (SFD is in negative mode), RSEL is unused since there is only one range in
this mode.
RSEL1
Bottom of Range
0
1 V
1
2 V
FS1
FS0
0
0
0
1
1
0
1
1
Table 7. Register 0xA2, 0xAA BSnUVTH
(Power-On Default 0x00)
Bit
Name
7–0
UV7–UV0
Table 8. Register 0xA3, 0xAB BSnUVHYST
(Power-On Default 0x00)
Bit
Name
7–5
Reserved
4–0
HY4–HY0
Sign of Detection Range
Positive
Negative
GF0
0
1
0
1
0
1
0
1
Top of Range
3 V
6 V
Fault Select Type
Overvoltage
Undervoltage
Out-of-Window
Not Allowed
Rev. B | Page 15 of 52
ADM1060
R/W
Description
R/W
8-Bit Digital Value for UV Thresh-
old on BSn SFD
R/W
Description
N/A
Cannot Be Used
R/W
5-Bit Digital Value for Hysteresis
on UV Threshold of BSn SFD
Glitch Filter Delay (µs)
0
5
10
20
30
50
75
100
Step Size (mV)
7.8
15.6
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