Voltage Monitor 0 Control Register (Vw0C) - Renesas M16C/64C User Manual

M16C/64C Group
7.2.5

Voltage Monitor 0 Control Register (VW0C)

Voltage Monitor 0 Control Register
b7 b6 b5 b4 b3 b2 b1
1 1 0 0 0 1
Notes:
1. This is the reset value when the LVDAS bit of address OFS1 is 1 during hardware reset.
2. This is the reset value after voltage monitor 0 reset, power-on reset, and when the LVDAS bit of address OFS1 is 0
during hardware reset.
Set the PRC3 bit in the PRCR register to 1 (write enabled) before rewriting to this register.
This register does not change at voltage monitor 1 reset, voltage monitor 2 reset, oscillator stop detect
reset, watchdog timer reset, or software reset.
VW0C0 (Voltage monitor 0 reset enable bit) (b0)
The VW0C0 bit is enabled when the VC25 bit in the VCR2 register is 1 (voltage detector 0 enabled).
Set the VW0C0 bit to 0 (disabled) when the VC25 bit is 0 (voltage detector 0 disabled).
Bit 6
When the LVDAS bit in the OFS1 address is 1, this bit becomes 0 after hardware reset. When using
voltage monitor 0 reset, set this bit to 1.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
b0
Symbol
VW0C
Bit Symbol Bit Name
Voltage monitor 0 reset
VW0C0
enable bit
—
Reserved bit
(b1)
—
Reserved bit
(b2)
—
Reserved bit
(b3)
—
Reserved bits
(b5-b4)
—
Reserved bits
(b7-b6)
Address
002Ah
0 : Disabled
1 : Enabled
Set to 1.
Set to 0.
When read, the read value is undefined.
When read, the read value is undefined.
Set to 0
Set to 1
7. Voltage Detector
Reset Value
(1)
1000 XX10b
(2)
1100 XX11b
Function
Page 67 of 807
RW
RW
RW
RW
RO
RW
RW