Frequency Divider; Register Configuration; Division Control Register (Divcr) - Renesas F-ZTAT H8 Series Hardware Manual

Section 20 Clock Pulse Generator
20.5

Frequency Divider

The frequency divider divides the duty-adjusted clock signal to generate the system clock (φ). The
frequency division ratio can be changed dynamically by modifying the value in DIVCR, as
described below. Power consumption in the chip is reduced in almost direct proportion to the
frequency division ratio. The system clock generated by the frequency divider can be output at the
φ pin.
20.5.1

Register Configuration

Table 20.4 summarizes the frequency division register.
Table 20.4 Frequency Division Register
Address* Name
H'FF5D Division control register
Note: * The lower 16 bits of the address are shown.
20.5.2

Division Control Register (DIVCR)

DIVCR is an 8-bit readable/writable register that selects the division ratio of the frequency
divider.
Bit 7
—
Initial value 1
Read/Write —
DIVCR is initialized to H'FC by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 2—Reserved: Read-only bits, always read as 1.
Rev. 7.00 Sep 21, 2005 page 660 of 878
REJ09B0259-0700
Abbreviation
DIVCR
6 5 4
— — —
1 1 1
— — —
Reserved bits
R/W
R/W
3 2 1
— — DIV1
1 1 0
— — R/W
Divide bits 1 and 0
These bits select the
frequency division ratio
Initial Value
H'FC
0
DIV0
0
R/W