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M16C/64C Group
25.3.10 Data Transmit/Receive Examples
The data transmit/receive examples are described in this section. The conditions for the examples are
as follows:
•
Slave address: 7 bits
•
Data: 8 bits
•
ACK clock
•
Standard clock mode, bit rate: 100 kbps (fIIC: 20 MHz; fVIIC: 4 MHz)
•
In receive mode, an ACK is returned for received data other than the last data. NACK is returned
after the last data is received.
•
When receiving data, I
•
Stop condition interrupt: enabled
•
Timeout detect interrupt: disabled
•
Set an own slave address to the S0D0 register (registers S0D1 or S0D2 should not be used)
When enabling an I
a receiver can determine whether to generate ACK or NACK after checking the received data each
byte.
25.3.10.1 Initial Settings
Follow the initial setting procedures below for 25.3.10.2 to 25.3.10.5.
(1) Write an own slave address to bits SAD6 to SAD0 in the S0D0 register.
(2) Write 85h to the S20 register (CCR value: 5, standard clock mode, ACK clock presents).
(3) Write 18h to the S4D0 register (fVIIC: fIIC divided-by-5, timeout interrupt disabled).
(4) Write 01h to the S3D0 register (stop condition detect interrupt enabled and I
eighth clock is disabled when receiving data).
(5) Write 0Fh to the S10 register (slave receive mode).
(6) Write 98h to the S2D0 register (SSC value: 18h; start/stop condition generation timing: long
mode).
(7) Write 08h to the S1D0 register (bit counter: 8, I
2
level: I
C-bus input).
If the MCU uses a single-master system and it is a master, start the initial setting procedures from
step (2).
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
20 MHz (fIIC) divided-by-5 = 4 MHz (fVIIC),
4 MHz (fVIIC) divided-by-8 and further divided-by-5 = 100 kbps (bit rate)
2
C-bus interrupt at the eighth clock (just before ACK clock): disabled
2
C-bus interrupt at the eighth clock (just before ACK clock) during data reception,
25. Multi-master I
2
C interface enabled, addressing format, input
2
C-bus Interface
2
C-bus interrupt at
Page 573 of 807
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