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4.8 BCU-Related Register Setting Examples
Figure 4-12 shows a BPC, BSC, BEC, and BHC register setting example, the corresponding settings for each CSn
area, and the memory map when the data area has been set according to the contents of the example shown in
Figure 4-3 CSC0 and CSC1 Register Setting Example (64 MB Mode) (n = 7 to 0).
Figure 4-12. BPC, BSC, BEC, BHC Register Setting Example (1/3)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BPC
1
0
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BSC
1
0
1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BEC
0
1
0
CHAPTER 4 BCU
(a) BPC register setting
0 1 0 0 1 0 0 0 0 0
(b) BSC register setting
0 0 1 0 1 0 0 0 0 1
(c) BEC register setting
0 0 0 0 0 0 1 0 0 0
Preliminary User's Manual A14874EJ3V0UM
0
0
0
Programmable peripheral I/O area
starting address: 2400000H
Programmable peripheral I/O area:
Can be accessed
0
1
0
VSB data bus size of CSn area
CS0 area: 32 bits
CS1 area: 32 bits
CS2 area: 8 bits
CS3 area: 8 bits
CS4 area: 16 bits
CS5 area: 16 bits
CS6 area: 32 bits
CS7 area: 32 bits
0
0
0
Endian format of CSn area
CS0 area: Little endian
CS1 area: Little endian
CS2 area: Little endian
CS3 area: Big endian
CS4 area: Little endian
CS5 area: Little endian
CS6 area: Little endian
CS7 area: Big endian
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