Dma Setting Examples; Setting Example 1 (Register Mode/Hardware Request) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
9.8

DMA Setting Examples

Setting examples applicable when DMA transfer is executed using the direct memory access controller are shown in the
following.
The transfer conditions for these setting examples are as follows.
Table 9.21 Transfer Condition List for DMA Transfer Setting Examples
Setting example 1
Setting example 2
Setting example 3
Setting example 4
For details of the settings, see the individual setting examples.
9.8.1

Setting Example 1 (Register Mode/Hardware Request)

The following table shows a setting example applicable when DMA transfer is executed using the settings shown below.
Table 9.22 DMA Transfer Setting Example 1
Item
Channel used
DMA mode
Transfer mode
Register set used
Source/destination
Start address
Address direction
Data size
DMA transfer byte count
DMA transfer request
DMAACK signal
DMA transfer end interrupt mask
CACHE setting
Setting example 1
N0SA = 1111_0000H (source address)
N0DA = 2222_0000H (destination address)
N0TB = 0000_0040H (transfer byte count)
CHCFG = 0002_2123H (configuration)
CHITVL = 0000_0000H (interval)
CHEXT = 0000_0000H (CACHE setting)
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
DMA Mode
Register
Register
Register
(continuous execution)
Link
Description
3
Register
Single transfer
Next0
Source
1111_0000H
Increment
32 bits
64 bytes
Rising edge detection by hardware
Level output during read
Not masked
Default value
9. Direct Memory Access Controller
Transfer Mode
Single
Block
Block
Block
Destination
2222_0000H
Increment
32 bits
Transfer Request
Hardware
Software
Software
Software
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