Dram Control Register (Dramcr) - Renesas H8S/2368 Series Hardware Manual

6.3.8

DRAM Control Register (DRAMCR)

DRAMCR is used to make DRAM/synchronous DRAM interface settings.
Note: The DRAM interface is not supported by the H8S/2366.
Bit Bit Name
15 OEE
14 RAST
−
13
12 CAST
−
11
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
OE Output Enable
The OE signal used when EDO page mode
DRAM is connected can be output from the
(OE) pin. The OE signal is common to all areas
designated as DRAM space.
0: OE signal output disabled
(OE) pin can be used as I/O port
1: OE signal output enabled
RAS Assertion Timing Select
Selects whether, in DRAM access, the RAS
signal is asserted from the start of the T
(rising edge of φ) or from the falling edge of φ.
Figure 6.4 shows the relationship between the
RAST bit setting and the RAS assertion timing.
The setting of this bit applies to all areas
designated as DRAM space.
0: RAS is asserted from φ falling edge in T
cycle
1: RAS is asserted from start of T
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Column Address Output Cycle Number Select
Selects whether the column address output
cycle in DRAM access comprises 3 states or 2
states. The setting of this bit applies to all areas
designated as DRAM space.
0: 2-state column address output cycle
1: 3-state column address output cycle
Reserved
Though this bit can be read from or written to,
the write value should always be 0.
Rev. 2.00, 05/03, page 123 of 820
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