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RM0453
3.4.7
Interrupts
TZIC is a secure peripheral that generates systematically an illegal access event when
accessed by a non-secure access.
TZSC is a security-aware peripheral, meaning that secure and non-secure registers
co-exist.
3.5
GTZC TZSC registers
All GTZC TZSC registers are accessed only by words (32-bit). Halfwords (16-bit) and bytes
(8-bit) accesses are denied and generate a bus error.
The TZSC MPCWM privileged control registers MPCWMn_UPWMR from the different
internal memories are defined in the table below.
MPCWM
index
1
2
3
3.5.1
GTZC TZSC control register (GTZC_TZSC_CR)
Address offset: 0x000
Reset value: 0x0000 0000
Secure read and write access only
Note:
When the system is non-secure (ESE = 0), this register cannot be written and is read zero.
31
30
29
Res.
Res.
Res.
Res.
15
14
13
Res.
Res.
Res.
Res.
Bits 31:1 Reserved, must be kept at reset value.
Bit 0 LCK: Lock the configuration of TZSC registers until next reset
Table 8. TZSC privileged MPCWMn register memory allocation
Memory
Unprivileged and unprivileged writable control (security controlled by user
Flash
option)
SRAM1
Unprivileged control (security controlled by user option)
SRAM2
Unprivileged control (security controlled by user option)
28
27
26
25
Res.
Res.
Res.
12
11
10
9
Res.
Res.
Res.
The configuration is unlocked after a wake-up from Standby.
This bit is unset by default and once set, it cannot be reset until a global TZSC reset.
0: All TZSC registers not locked
1: All TZSC registers locked
Description
24
23
22
Res.
Res.
Res.
8
7
6
Res.
Res.
Res.
RM0453 Rev 5
Global security controller (GTZC)
21
20
19
18
Res.
Res.
Res.
Res.
5
4
3
2
Res.
Res.
Res.
Res.
17
16
Res.
Res.
1
0
Res.
LCK
rs
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