ST STM32L4+ Series Reference Manual page 1294

Advanced-control timers (TIM1/TIM8)
37.4.30 TIM8 option register 2 (TIM8_OR2)
Address offset: 0x60
Reset value: 0x0000 0001
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
ETRSEL[1:0] Res. Res.
rw rw
Bits 31:17 Reserved, must be kept at reset value.
Bits 16:14 ETRSEL[2:0]: ETR source selection
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 BKCMP2P: BRK COMP2 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 10 BKCMP1P: BRK COMP1 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 9 BKINP: BRK BKIN input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
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27 26 25
Res. Res. Res.
11 10 9
BK BK
CMP2 CMP1 BKINP
P P
rw rw rw
These bits select the ETR input source.
000: ETR input is connected to I/O
001: Reserved
010: COMP2 output
Others: Reserved
bits in TIMx_BDTR register).
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP2 input is active high
1: COMP2 input is active low
in TIMx_BDTR register).
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP1 input is active high
1: COMP1 input is active low
in TIMx_BDTR register).
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
0: BKIN input is active high
1: BKIN input is active low
in TIMx_BDTR register).
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
BKDF1
Res. Res. Res.
BK2E
rw
RM0432 Rev 6
20 19 18
Res. Res. Res.
4 3 2
BK
Res. Res.
CMP2E CMP1E
rw
RM0432
17 16
ETRSEL
Res.
[2]
rw
1 0
BK
BKINE
rw rw