ST STM32L4+ Series Reference Manual page 1288

Advanced-control timers (TIM1/TIM8)
Bits 31:5 Reserved, must be kept at reset value.
Bit 4 TI1_RMP: Input Capture 1 remap
Bits 3:2 Reserved, must be kept at reset value.
Bits 1:0 ETR_ADC2_RMP: External trigger remap on ADC2 analog watchdog
Note: ADC2 AWDx sources are 'ORed' with the TIM8_ETR input signals. When ADC2 AWDx
37.4.25 TIMx capture/compare mode register 3
(TIMx_CCMR3)(x = 1, 8)
Address offset: 0x54
Reset value: 0x0000 0000
The channels 5 and 6 can only be configured in output.
Output compare mode:
31 30 29
Res. Res. Res. Res.
15 14 13
OC6
OC6M[2:0]
CE
rw rw rw
Bits 31:25 Reserved, must be kept at reset value.
Bits 23:17 Reserved, must be kept at reset value.
Bit 15 OC6CE: Output compare 6 clear enable
Refer to OC1CE description.
Bits 24, 14, 13, 12 OC6M[3:0]: Output compare 6 mode
Refer to OC1M description.
Bit 11 OC6PE: Output compare 6 preload enable
Refer to OC1PE description.
Bit 10 OC6FE: Output compare 6 fast enable
Refer to OC1FE description.
Bits 9:8 Reserved, must be kept at reset value.
Bit 7 OC5CE: Output compare 5 clear enable
Refer to OC1CE description.
1288/2301
0: TIM8 input capture 1 is connected to I/O
1: TIM8 input capture 1 is connected to COMP2 output.
00: TIM8_ETR is not connected to ADC2 AWDx. This configuration must be selected when
the ETR comes from the I/O.
01: TIM8_ETR is connected to ADC2 AWD1.
10: TIM8_ETR is connected to ADC2 AWD2.
11: TIM8_ETR is connected to ADC2 AWD3.
is used, it is necessary to make sure that the corresponding TIM8_ETR input pin is not
enabled in the alternate function controller. Refer to
circuitry.
28 27 26 25
Res. Res. Res.
12 11 10 9
OC6
OC6FE Res.
PE
rw rw rw
24 23 22
OC6M[3] Res. Res.
rw
8 7 6
OC5
Res. OC5M[2:0]
CE
rw rw
RM0432 Rev 6
Figure 306: TIM8 ETR input
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
OC5PE OC5FE
rw rw rw rw
RM0432
17 16
Res. OC5M[3]
rw
1 0
Res. Res.