ST STM32L4+ Series Reference Manual page 1292

Advanced-control timers (TIM1/TIM8)
Bit 1 BKCMP1E: BRK COMP1 enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 0 BKINE: BRK BKIN input enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Note: Refer to
overview.
37.4.29 TIM1 option register 3 (TIM1_OR3)
Address offset: 0x64
Reset value: 0x0000 0001
31 30 29 28
Res. Res. Res. Res.
15 14 13 12
Res. Res. Res. Res.
Bits 31:12 Reserved, must be kept at reset value.
Bit 11 BK2CMP2P: BRK2 COMP2 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 10 BK2CMP1P: BRK2 COMP1 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
1292/2301
This bit enables the COMP1 for the timer's BRK input. COMP1 output is 'ORed' with the
other BRK sources.
0: COMP1 input disabled
1: COMP1 input enabled
in TIMx_BDTR register).
This bit enables the BKIN alternate function input for the timer's BRK input. BKIN input is
'ORed' with the other BRK sources.
0: BKIN input disabled
1: BKIN input enabled
in TIMx_BDTR register).
Figure 305: TIM1 ETR input circuitry
27 26 25
Res. Res. Res.
11 10 9
BK2 BK2
BK2
CMP2 CMP1
INP
P P
rw rw rw
This bit selects the COMP2 input sensitivity. It must be programmed together with the BK2P
polarity bit.
0: COMP2 input is active low
1: COMP2 input is active high
in TIMx_BDTR register).
This bit selects the COMP1 input sensitivity. It must be programmed together with the BK2P
polarity bit.
0: COMP1 input is active low
1: COMP1 input is active high
in TIMx_BDTR register).
and to
24 23 22 21
Res. Res. Res. Res.
8 7 6 5
BK2DF1
Res. Res. Res.
BK1E
rw
RM0432 Rev 6
Figure 327: Break and Break2 circuitry
20 19 18
Res. Res. Res.
4 3 2
BK2
Res. Res.
CMP2E
rw
RM0432
17 16
Res. Res.
1 0
BK2
BK2INE
CMP1E
rw rw