ST STM32L4+ Series Reference Manual page 1291

RM0432
Bits 16:14 ETRSEL[2:0]: ETR source selection
Note: These bits can not be modified as long as LOCK level 1 has been programmed (LOCK
Bits 13:12 Reserved, must be kept at reset value.
Bit 11 BKCMP2P: BRK COMP2 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 10 BKCMP1P: BRK COMP1 input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 9 BKINP: BRK BKIN input polarity
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bit 8 BKDF1BK0E: BRK dfsdm1_break[0] enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
Bits 7:3 Reserved, must be kept at reset value.
Bit 2 BKCMP2E: BRK COMP2 enable
Note: This bit can not be modified as long as LOCK level 1 has been programmed (LOCK bits
These bits select the ETR input source.
000: ETR input is connected to I/O
001: COMP1 output
010: COMP2 output
Others: Reserved
bits in TIMx_BDTR register).
This bit selects the COMP2 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP2 input is active high
1: COMP2 input is active low
in TIMx_BDTR register).
This bit selects the COMP1 input sensitivity. It must be programmed together with the BKP
polarity bit.
0: COMP1 input is active high
1: COMP1 input is active low
in TIMx_BDTR register).
This bit selects the BKIN alternate function input sensitivity. It must be programmed together
with the BKP polarity bit.
0: BKIN input is active high
1: BKIN input is active low
in TIMx_BDTR register).
This bit enables the dfsdm1_break[0] for the timer's BRK input. dfsdm1_break[0] output is
'ORed' with the other BRK sources.
0: dfsdm1_break[0] input disabled
1: dfsdm1_break[0] input enabled
in TIMx_BDTR register).
This bit enables the COMP2 for the timer's BRK input. COMP2 output is 'ORed' with the
other BRK sources.
0: COMP2 input disabled
1: COMP2 input enabled
in TIMx_BDTR register).
Advanced-control timers (TIM1/TIM8)
RM0432 Rev 6 1291/2301
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