ST STM32L4+ Series Reference Manual page 1290

Advanced-control timers (TIM1/TIM8)
Bit 29 GC5C1: Group Channel 5 and Channel 1
Note: it is also possible to apply this distortion on combined PWM signals.
Bits 28:16 Reserved, must be kept at reset value.
Bits 15:0 CCR5[15:0]: Capture/Compare 5 value
37.4.27 TIMx capture/compare register 6 (TIMx_CCR6)(x = 1, 8)
Address offset: 0x5C
Reset value: 0x0000
15 14 13
rw rw rw
Bits 15:0 CCR6[15:0]: Capture/Compare 6 value
37.4.28 TIM1 option register 2 (TIM1_OR2)
Address offset: 0x60
Reset value: 0x0000 0001
31 30 29
Res. Res. Res. Res.
15 14 13
ETRSEL[1:0] Res. Res.
rw rw
Bits 31:17 Reserved, must be kept at reset value.
1290/2301
Distortion on Channel 1 output:
0: No effect of OC5REF on OC1REFC5
1: OC1REFC is the logical AND of OC1REFC and OC5REF
This bit can either have immediate effect or be preloaded and taken into account after an
update event (if preload feature is selected in TIMxCCMR1).
CCR5 is the value to be loaded in the actual capture/compare 5 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC5PE). Else the preload value is copied in the active capture/compare 5 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC5 output.
12 11 10 9
rw rw rw rw
CCR6 is the value to be loaded in the actual capture/compare 6 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register
(bit OC6PE). Else the preload value is copied in the active capture/compare 6 register when
an update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signaled on OC6 output.
28 27 26 25
Res. Res. Res.
12 11 10 9
BK BK
BKINP
CMP2P CMP1P
rw rw rw
8 7 6
CCR6[15:0]
rw rw rw
24 23 22
Res. Res. Res.
8 7 6
BKDF1
Res. Res.
BK0E
rw
RM0432 Rev 6
5 4 3 2
rw rw rw rw
21 20 19 18
Res. Res. Res. Res.
5 4 3 2
BK
Res. Res. Res.
CMP2E
rw
RM0432
1 0
rw rw
17 16
ETR
Res. SEL
[2]
rw
1 0
BK
BKINE
CMP1E
rw rw