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Under development
Preliminary specification
Specifications in this manual are tentative and subject to change.
M16C/26 Group
1.3 Precautions for Interrupts
1.3.1 Reading address 00000
Do not read the address 00000
reads interrupt information (interrupt number and interrupt request priority level) from the address
00000
during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to "0".
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If the address 00000
among the enabled interrupts is cleared to "0". This causes a problem that the interrupt is canceled, or an
unexpected interrupt request is generated.
1.3.2 Setting the SP
Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to '0000
after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-
gram may go out of control.
Especially when using NMI interrupt, set a value in the ISP at the beginning of the program. For the first
and only the first instruction after reset, all interrupts including NMI interrupt are disabled.
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1.3.3 The NMI Interrupt
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1. The NMI interrupt is invalid after reset. The NMI interrupt becomes effective by setting to "1" the PM24
bit of the PM2 register. Once enabled, it stays enabled until a reset is applied.
2. The input level of the NMI pin can be read by accessing the P8 register's P8_5 bit. Note that the P8_5
bit can only be read when determining the pin level in NMI interrupt routine.
3. When selecting NMI function, stop mode cannot be entered into while input on the NMI pin is low. This
is because while input on the NMI pin is low the CM1 register's CM10 bit is fixed to "0".
4. When selecting NMI function, do not go to wait mode while input on the NMI pin is low. This is because
when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current
consumption in the chip does not drop. In this case, normal condition is restored by an interrupt gener-
ated thereafter.
5. When selecting NMI function, the low and high level durations of the input signal to the NMI pin must
each be 2 CPU clock cycles + 300 ns or more.
Rev.0.90
2003.12.28
page 3 of 28
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in a program. When a maskable interrupt request is accepted, the CPU
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is read in a program, the IR bit for the interrupt which has the highest priority
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1.3 Precautions for Interrupts
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