Non-Maskable Interrupts (Nmi) - Renesas NU85E Preliminary User's Manual

8.2 Non-Maskable Interrupts (NMI)

A non-maskable interrupt request (NMI) is acknowledged unconditionally even if the NU85E is in an interrupt
disabled (DI) state.
A non-maskable interrupt request is generated according to DCNMIn pin input (n = 2 to 0). When a rising edge is
input to the DCNMIn pin, a non-maskable interrupt (NMIn) is generated.
If multiple non-maskable interrupts are generated at the same time, the highest priority servicing is executed
according to the following priority order (the lower priority interrupts are ignored).
NMI2 > NMI1 > NMI0
Note that if an NMI0, NMI1, or NMI2 request is generated while NMI0 is being serviced, the servicing is executed
as follows.
(1) If an NMI0 request is generated while NMI0 is being serviced
The new NMI0 request is held pending regardless of the value of the PSW's NP bit. The pending NMI0
request is acknowledged after servicing of the current NMI0 request has finished (after execution of the RETI
instruction).
(2) If an NMI1 request is generated while NMI0 is being serviced
If the PSW's NP bit remains set (1) while NMI0 is being serviced, the new NMI1 request is held pending. The
pending NMI1 request is acknowledged after servicing of the current NMI0 request has finished (after
execution of the RETI instruction).
If the PSW's NP bit is cleared (0) while NMI0 is being serviced, the newly generated NMI1 request is
executed (NMI0 servicing is halted).
(3) If an NMI2 request is generated while NMI0 is being serviced
The new NMI2 request is executed, regardless of the value of the PSW's NP bit (NMI0 servicing is halted).
Cautions 1. When a non-maskable interrupt request (NMI) is generated, the values of the PC and
PSW are saved in the registers (FEPC and FEPSW) for saving the status when an NMI
occurs, but in this case, only NMI0 can be normally restored by the RETI instruction.
Even if NMI1 and NMI2, which assume an emergency use such as watchdog, are
restored by the RETI instruction, the INTC cannot determine the priority of the following
interrupts. Therefore, when NMI1 or NMI2, and other maskable interrupts are input with
a miniscule time lag, maskable interrupt requests other than NMI1 and NMI2 may be
deleted.
When NMI1 or NMI2 is generated while NMI0 is being serviced, FEPC is overwritten.
When NMI0 servicing has been restored after the NMI1 and NMI2 servicing, the main
routine cannot successfully be restored from the NMI0 servicing and an endless loop
occurs. In the case of NMI2, a newly generated NMI2 request is executed regardless of
the value of the NP bit in the PSW.
Therefore, NMI1 and NMI2 cannot be restored.
2. If interrupt servicing by NMI1 or NMI2 is continued without the RETI instruction being
executed, hang up will not occur, but none of the following interrupt requests will be
acknowledged because multiple interrupts are disabled.
CHAPTER 8 INTC
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