Interrupts In Ram - Renesas FSL-T06 User Manual

Flash Self-Programming Library
Figure 4-5

4.5 Interrupts in RAM

R01US0046ED Rev. 1.01
User Manual
This sequence is best for devices with sufficient internal RAM. User code
execution is always possible during Self-Programming, because a Flash
operation is just initiated by the FSL command. While the FSL returns control to
the user application, the Flash operation is executed in background. The user
has to poll the command status via the status check function. Interrupt as well as
user code execution is possible if all related functions are located in RAM.
To enable this mode, the library must be configured to use the user mode (see
5.1 Pre-compile configuration).
Internal mode
Only small parts of the library are executed in RAM, the rest is executed in the
Code Flash. Frequent activation and deactivation of the Flash Environment is
necessary and therefore programming time will increase.
Firmware
Firmware Interface
FSL User Interface
User Control Program
User Application
Basic RAM saving reprogramming sequence
Less internal RAM is used as only the device firmware interface need to be
executed in RAM. On the other hand, normal user code execution during Self-
Programming is impossible, because a FSL function starting a command does
not return until the operation is finished. Therefore only interrupts are possible
during Self-Programming.
To enable this mode, the library must be configured to use the internal mode (see
5.1 Pre-compile configuration).
As mentioned before, Code Flash is not accessible during Self-Programming.
Therefore the interrupt vector table as well as interrupt handler routines, which
are normally located in the Flash, are not accessible. Interrupt vectors and
handler routines have to be re-routed to not affected memory like external or
internal RAM.
Two methods exist to execute interrupts from RAM:

Single interrupt vector
All interrupts are mapped to the single interrupt vector of interrupt
channel 0. Based on this interrupt, the interrupt handler routine has to
handle all pending interrupts.

Interrupt table mapped to RAM
The base address of the interrupt vector table is mapped to a different
location in RAM. In this case the offset of the different channels is added
to the new base address.
No Flash No Flash
Access Access
possible
possible
FSL Usage
Execution
in RAM
...
Execution
in Flash
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