System Control Register (Syscr); Notes On Register Access - Renesas Hitachi H8S/2194 Series Hardware Manual

18.2.3

System Control Register (SYSCR)

Bit :
7
—
Initial value :
0
R/W : —
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 6.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
Bit 3: External Reset (XRST)
Indicates the reset source. When the watchdog timer is used, a reset can be generated by
watchdog timer overflow in addition to external reset input. XRST is a read-only bit. It is set to
1 by an external reset, and cleared to 0 by watchdog timer overflow.
Bit 3
XRST Description
0 Reset is generated by watchdog timer overflow
1 Reset is generated by external reset input
18.2.4

Notes on Register Access

The watchdog timer's WTCNT and WTCSR registers differ from other registers in being more
difficult to write to. The procedures for writing to and reading these registers are given below.
(1) Writing to WTCNT and WTCSR
These registers must be written to by a word transfer instruction. They cannot be written to
with byte transfer instructions.
Figure 18.2 shows the format of data written to WTCNT and WTCSR. WTCNT and
WTCSR both have the same write address. For a write to WTCNT, the upper byte of the
written word must contain H'5A and the lower byte must contain the write data. For a write
to WTCSR, the upper byte of the written word must contain H'A5 and the lower byte must
contain the write data. This transfers the write data from the lower byte to WTCNT or
WTCSR.
6 5 4
— INTM1 INTM0
0 0 0
— R R/W
3 2
XRST NMIEG1 NMIEG0
1 0
R R/W R/W
Rev. 2.0, 11/00, page 397 of 1037
1 0
—
0 1
—
(Initial value)