Pin Configuration; Register Configuration - Renesas Hitachi H8S/2194 Series Hardware Manual

7.2.4

Pin Configuration

The flash memory is controlled by means of the pins shown in table 7.2.
Table 7.2 Flash Memory Pins
Pin Name
Reset
Flash write enable
Mode 0
Port 12
Port 13
Port 14
Transmit data
Receive data
7.2.5

Register Configuration

The registers used to control the on-chip flash memory when enabled are shown in table 7.3.
In order to access these registers, the FLSHE bit in STCR must be set to 1.
Table 7.3 Flash Memory Registers
Register Name
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
Serial timer control register
Notes: 1. When the FWE bit in FLMCR1 is not set at 1, writes are disabled.
2. When a high level is input to the FWE pin, the initial value is H'80.
3. When a low level is input to the FWE pin, or if a high level is input and the SWE bit in
FLMCR1 is not set, these registers are initialized to H'00.
4. FLMCR1, FLMCR2, EBR1, and EBR2 are 8-bit registers. Only byte accesses are
valid for these registers, the access requiring 2 states.
5. Lower 16 bits of the address.
Rev. 2.0, 11/00, page 130 of 1037
Abbreviation I/O
5(6
Input
FWE Input
MD0 Input
P12 Input
P13 Input
P14 Input
SO1 Output
SI1 Input
Abbreviation
FLMCR1
FLMCR2
*4
EBR1
*4
EBR2
STCR
Function
Reset
Flash program/erase protection by hardware
Sets this LSI operating mode
Sets this LSI operating mode when MD0 = 0
Sets this LSI operating mode when MD0 = 0
Sets this LSI operating mode when MD0 = 0
Serial transmit data output
Serial receive data input
Initial
R/W Value
*4 *1
R/W H'00
*4 *1
R/W H'00
*1
R/W H'00
*1
R/W H'00
R/W H'00
Access
*5
Address Size
*2
H'FFF8 8
*3
H'FFF9 8
*3
H'FFFA 8
*3
H'FFFB 8
H'FFEE 8