Renesas Hitachi H8S/2194 Series Hardware Manual page 640

PPG0 to 7/ PPG0 to 7/
(P70 to 77) (P70 to 77)
PR0 to 7/ PR0 to 7/
(P60 to 67) (P60 to 67)
EXTTRG/(P80)
Csync
4-head
COMP(PS2)
special
C.ROTARY(PS0)
playback
H.Amp SW(PS1)
controller
Additional
V pulse
Vpulse
generator
Head-switch
AUDIOFF
timing
VIDEOFF
generator
DPG(PS3)
Noise
Det.
DFG
Speed
error
detector
DRM
PWM
PWM
CA P
PWM
PWM
Frequency
CFG
divider
SV1(P82)
( )
SV2(P83)
( )
EXCTL(PS4)
)
CTLFB
+ -
CTL Amp
Gain control
by register
- +
setting
CTL
+
Head
CTL
-
Head
EXCAP(P81)
Figure 28.1 Block Diagram of Servo Circuits
Sync
detector
VD
REC:ON
XE:ON
ADTRIG
(HSW)
Phase
Ep
error
detector
Es
+
Digital
filter
Gain up.
Digital
filter
Gain up.
Speed
DVCFG Es
error
detector
DVCFG2
REC
Phase
Ep
error
detector
PB.ASM
(NTSC)
Frequency
PB.
divider
REC
ASM
(PAL)
PB.CTL
VISS
circuit
DutyI/O
(Duty deter-
minator)
REC-CTL
System
clock
Capstan
Res Drum system
system
reference
reference
signal signal
Digital
filter
+
+
+
Digital
filter
X-value
adjustment
REF30X
REC-CTL
generator
(Assemble
recording)
Rev. 2.0, 11/00, page 613 of 1037
A/D
AN pins
converter
Timer X1
Timer L
Timer R