Renesas Hitachi H8S/2194 Series Hardware Manual page 694

Bit 6: DFG Counter Clear Bit (CCLR)
Enforces clearing of the 5-bit counter which counts DFG by software. Writing 1 returns 0
immediately. Writing 0 causes no effect on operation.
Bit 6
CCLR Description
0 Normal operation
1 Clears the 5-bit DFG counter
Bit 5: 16-bit Timer Counter Clock Source Selection Bit (CKSL)
Selects the clock source of the 16-bit timer counter.
Bit 5
CKSL Description
φs/4
0
φs/8
1
Bits 4 to 0: FIFO1 Output Timing Setting Bits (DFCRA4 to DFCRA0)
Determine the starting point of the timing of FIFO1. The initial value is undetermined. Be sure
to set a value after a reset or stand-by. It is valid only if bit 7 (FRT bit) of HSM2 is 0.
(9) DFG Reference Register 2 (DFCRB)
Bit : 7
—
Initial value :
1
—
R/W :
Note: * Undetermined
DFCRB is a register which determines the starting point of the timing of FIFO2.
DFCRB is an 8-bit write-only register. If a read is attempted, an undetermined value is read out.
Bits 7 to 5 are reserved. No write is valid. If a read is attempted, 1 is read out. It is not
initialized by a reset or stand-by, accordingly be sure to write data before use.
Bits 4 to 0: FIFO2 Output Timing Setting Bits (DFCRB4 to DFCRB0)
Determine the starting of the FIFO2 output. The initial values are undetermined, accordingly be
sure to write values in the bits after a reset or stand-by.
It is valid only if bit 7 (FRT bit) of HSM2 is 0.
6 5 4
— —
DFCRB4 DFCRB3 DFCRB2 DFCRB1
*
1 1
— —
W
3 2 1
* * *
W W W
Rev. 2.0, 11/00, page 667 of 1037
(Initial value)
(Initial value)
0
DFCRB0
*
W