28.12.5 Additional V Pulse Signal - Renesas Hitachi H8S/2194 Series Hardware Manual

28.12.5 Additional V Pulse Signal

Figure 28.44 shows the additional V pulse signal. The Mlevel and Vpulse signals are generated
by the head-switch timing generator. The OSCH signal is combined with these to produce
equalizing pulses. The polarity can be selected by the POL bit in the additional V register
(ADDVR). The Vpulse pin outputs a low level by a reset, and in standby mode and module stop
mode.
· ADDVR
VPON
OSCH
Vpulse
Mlevel
[Legend]
STBY : Power-down mode signal
Vpulse, Mlevel : Signal from the HSW timing generator
Rs : Voltage division resistance (20 k : Reference value)
Internal bus
R/W R/W R/W
CUT HMSK POL
Figure 28.44 Additional V Pin
R/W R/W
· ADDVR
HiZ
Rev. 2.0, 11/00, page 743 of 1037
STBY
V V
CC CC
Rs
Vpulse pin
Rs
V V
SS SS