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29.2.4
Serial Interface Timing of HD64F2194, HD64F2194C
Table 29.7 Serial Interface Timing of HD64F2194, HD64F2194C
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless
otherwise specified.)
Item
Input clock cycle
Input clock pulse
width
Input clock rise time
Input clock fall time
Transmit data delay
time (clock sync)
Receive data setup
time (clock sync)
Receive data hold
time (clock sync)
Transmit data output
delay time
Receive data setup
time (clock sync)
Receive data hold
time (clock sync)
&6
setup time
&6
hold time
Rev. 2.0, 11/00, page 830 of 1037
Applicable
Symbol
Pins
t
SCK1
scyc
SCK2
t
SCK1,
SCKW
SCK2
t
SCK1
SCKr
SCK2
t
SCK1
SCKf
SCK2
t
SO1
TXD
t
SI1
RXS
t
SI1
RXH
t
SO2
TXD
t
SI2
RXS
t
SI2
RXH
&6
t
CSS
&6
t
CSH
Values
Test Conditions Min
Asynchroniza-
4
tion
Clock
6
synchronization
2
0.4
100
100
180
180
1
1
Typ
Max
Unit
t
cyc
0.6
t
scyc
1.5
t
cyc
60
ns
1.5
t
cyc
60
ns
100
ns
ns
ns
200
ns
ns
ns
t
scyc
t
scyc
Figure
Figure
29.6
Figure
29.7
Figure
29.7
Figure
29.8
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