Block Diagram - Renesas Hitachi H8S/2194 Series Hardware Manual

17.1.2

Block Diagram

Figure 17.1 shows a block diagram of the Timer X1.
FTIA*
(HSW)
FTIB*
(VD)
FTIC*
(DVCTL)
FTID*
(NHSW)
(DVCFG)
/ 4
/ 16
/ 64
Output comparing output
FTOA
FTOB
[Legend]
TIER
TCSRX
FRC
OCRA
OCRB
TCRX
TOCR
ICRA
ICRB
ICRC
ICRD
Note: * stands for the external terminal.
( ) stands for the internal signal.
Rev. 2.0, 11/00, page 356 of 1037
Input
capture
control
: Timer interrupt enabling register
: Timer control/status register X
: Free running counter
: Output comparing register A
: Output comparing register B
: Timer control register X
: Output comparing control register
: Input capture register A
: Input capture register B
: Input capture register C
: Input capture register D
Figure 17.1 Block Diagram of the Timer X1
ICRA
ICRB
ICRC
ICRD
TCRX
OCRB
Comparison circuit
FRC
Comparison circuit
OCRA
TOCR
TCSRX
TIER
Interrupt
request 7