Renesas Hitachi H8S/2194 Series Hardware Manual page 423

Bit 3: Reset or NMI (RST/
Specifies whether an internal reset or NMI interrupt is requested on WTCNT overflow in
watchdog timer mode.
Bit 3
RST/ Description
1,0,
1,0,
0 An NMI interrupt request is generated
1 An internal reset request is generated
Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0)
These bits select an internal clock source, obtained by dividing the system clock (φ) for input to
WTCNT.
T T
WDT input clock selection
Bit 2 Bit 1
CSK2 CSK1
0 0
1
1 0
1
Note: * The overflow period is the time from when WTCNT starts counting up from H'00 until
overflow occurs.
Rev. 2.0, 11/00, page 396 of 1037
)
10, 10,
Bit 0 Description
CSK0 Clock
φ/2 (Initial
0
value)
φ/64
1
φ/128
0
φ/512
1
φ/2048
0
φ/8192
1
φ/32768
0
φ/131072
1
Overflow Period* (when φ = 10 MHz)
51.2 µs
1.6 ms
3.3 ms
13.1 ms
52.4 ms
209.7 ms
838.9 ms
3.36 s
(Initial value)