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(3) Servo Interrupt Request Register 1 (SIRQR1)
7
Bit :
IRRDRM3
Initial value :
0
R/(W) *
R/W :
Note: * Only 0 can be written to clear the flag.
SIRQR1 displays an occurrence of an interrupt request of the servo section. If the interrupt
request occurred, the corresponding bit is set to 1.
SIRQR1 is an 8-bit readable/writable register. Writing is allowed only in the case of writing 0 to
clear the flag. It is initialized to H'00 by a reset, stand-by or module stop.
Bit 7: Drum Phase Error Detector Interrupt Request Bit (IRRDRM3)
Bit 7
IRRDRM3
Description
0
No interrupt request from the drum phase error detector
1
Interrupt requested from the drum phase error detector
Bit 6: Drum Speed Error Detector (lock detection) Interrupt Request Bit (IRRDRM2)
Bit 6
IRRDRM2
Description
0
No interrupt request from the drum speed error detector (lock detection)
1
Interrupt requested from the drum speed error detector (lock detection)
Bit 5: Drum Speed Error Detector (OVF, latch) Interrupt Request Bit (IRRDRM1)
Bit 5
IRRDRM1
Description
0
No interrupt request from the drum speed error detector (OVF, latch) (Initial value)
1
Interrupt requested from the drum speed error detector (OVF, latch)
Rev. 2.0, 11/00, page 814 of 1037
6
5
IRRDRM2 IRRDRM1
IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
0
0
R/(W) *
R/(W) *
4
3
0
0
R/(W) *
R/(W) *
R/(W) *
2
1
0
0
0
0
R/(W) *
R/(W) *
(Initial value)
(Initial value)
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