Renesas Hitachi H8S/2194 Series Hardware Manual page 961

H'D064: FIFO Output Pattern Register 1 FPDRA: HSW Timing Generator
Bit :
15
—
Initial value :
1
R/W : —
Bit :
7
PPGA7
Initial value : *
W
R/W :
H'D066: FIFO Timing Pattern Register 1 FTPRA: HSW Timing Generator
15 14
Bit :
FTPRA15 FTPRA14
Initial value :
* *
R/W :
W W
H'D066: FIFO Timer Capture Register 1 FTCTR: HSW Timing Generator
15 14
Bit :
FTCTR15 FTCTR14
Initial value :
0 0
R/W :
R R
H'D068: FIFO Output Pattern Register 2 FPDRB: HSW Timing Generator
Bit :
15
—
Initial value :
1
—
R/W :
7
Bit :
PPGB7
*
Initial value :
W
R/W :
Note: * Undetermined
Rev. 2.0, 11/00, page 934 of 1037
14 13
ADTRGA STRIGA
* *
W W
6 5
PPGA6 PPGA5
* *
W W
13 12 11 10
FTPRA13 FTPRA12 FTPRA11 FTPRA10
* * * *
W W W W
13 12 11 10
FTCTR13 FTCTR12 FTCTR11 FTCTR10
0 0 0 0
R R R R
14 13
ADTRGB STRIGB
* *
W W
6 5
PPGB6 PPGB5
* *
W W
12 11
NarrowFFA VFFA
* *
W W
4 3
PPGA4 PPGA3
* *
W W
9 8 7 6
FTPRA9 FTPRA8 FTPRA7 FTPRA6
* * * *
W W W W
9 8 7 6
FTCTR9 FTCTR8 FTCTR7 FTCTR6
0 0 0 0
R R R R
12 11
NarrowFFB VFFB
* *
W W
4 3
PPGB4 PPGB3
* *
W W
10 9
AFFA VpulseA MlevelA
* *
W W
2 1
PPGA2 PPGA1 PPGA0
* *
W W
5 4 3 2
FTPRA5 FTPRA4 FTPRA3 FTPRA2
* * * *
W W W W
5 4 3 2
FTCTR5 FTCTR4 FTCTR3 FTCTR2
0 0 0 0
R R R R
10 9
AFFB VpulseB MlevelB
* *
W W
2 1
PPGB2 PPGB1 PPGB0
* *
W W
8
*
W
0
*
W
1 0
FTPRA1 FTPRA0
*
*
W W
1 0
FTCTR1 FTCTR0
0
0
R R
8
*
W
0
*
W