Initial Register Values - Renesas Hitachi H8S/2194 Series Hardware Manual

Bit 6: User Bit or Interrupt Mask Bit (UI)
Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC
instructions. This bit can also be used as an interrupt mask bit. For details, see section 6,
Interrupt Controller.
Bit 5: Half-Carry Flag (H)
When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is
executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0
otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the
H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When
the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to 0 otherwise.
Bit 4: User Bit (U)
Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC
instructions.
Bit 3: Negative Flag (N)
Stores the value of the most significant bit (sign bit) of data.
Bit 2: Zero Flag (Z)
Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Bit 1: Overflow Flag (V)
Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.
Bit 0: Carry Flag (C)
Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
(a) Add instructions, to indicate a carry
(b) Subtract instructions, to indicate a borrow
(c) Shift and rotate instructions, to store the carry
The carry flag is also used as a bit accumulator by bit-manipulation instructions.
Some instructions leave some or all of the flag bits unchanged. For the action of each
instruction on the flag bits, see section 29, Appendix A.1, List of Instructions.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional
branch (Bcc) instructions.
2.4.4

Initial Register Values

Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the
trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not
initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed
immediately after a reset.
Rev. 2.0, 11/00, page 27 of 1037