Renesas Hitachi H8S/2194 Series Hardware Manual page 757

(5) Drum System Digital Filter Control Register (DFIC)
Bit : 7
—
1
Initial value :
—
R/W :
Note: * Only 0 can be written
DFIC is an 8-bit readable/writable register that controls the status of the drum system digital
filter and operating mode. It can be accessed by byte access only. Word access gives unassured
results.
Bit 7 is a reserved bit. Writes are disabled. If read is attempted, an undetermined value is read
out. DFIC is initialized to H'80 by a reset, and in standby mode and module stop mode.
Bit 7: Reserved
Reads and writes are both disabled.
Bit 6: Drum System Range Over Flag (DROV)
This flag is set to 1 when the result of a drum system filter computation exceeds 12 bits in width.
To clear this flag, write 0.
Bit 6
DROV Description
0 Indicates that the filter computation result did not exceed 12 bits
1 Indicates that the filter computation result exceeded 12 bits
Bit 5: Drum Phase System Filter Computation Start Bit (DPHA)
Starts or stops filter processing for the drum phase system.
Bit 5
DPHA Description
0 Phase system filter computations are disabled
Phase computation result (Y) is not added to Es (see figure 28.39)
1 Phase system filter computations are enabled
Rev. 2.0, 11/00, page 730 of 1037
6 5
DROV DPHA DZPON
0 0
R/(W) *
R/(W)
4 3
DZSON DSG2
0 0
R/W R/W R/W
2 1 0
DSG1 DSG0
0 0 0
R/W R/W
(Initial value)
(Initial value)