Renesas Hitachi H8S/2194 Series Hardware Manual page 226

Increment
address
Notes: 1.
Preprogramming (setting erase block data to all 0) is not necessary.
2.
The values of x, y, z, , , , ,
3.
Verify data is read in 16-bit (word) units.
4.
Set only one bit in EBR1 or EBR2. More than one bit cannot be set.
5.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 8.13 Erase/Erase-Verify Flowchart (Single-Block Erase)
START
1
*
Set SWE bit in FLMCR1
Wait (x) µs
n = 1
Set EBR1, EBR2
Enable WDT
Set ESU bit in FLMCR1 or FLMCR2
Wait (y) µs
Set E bit in FLMCR1 or FLMCR2
Wait (z) ms
Clear E bit in FLMCR1 or FLMCR2
Wait ( ) µs
Clear ESU bit in FLMCR1 or FLMCR2
Wait ( ) µs
Disable WDT
Set EV bit in FLMCR1 or FLMCR2
Wait ( ) µs
Set block start address to
verify address
H'FF dummy write to verify address
Wait ( ) µs
Read verify data
NO
Verify data =
all 1?
YES
NO
Last address
of block?
YES
Clear EV bit in FLMCR1 or FLMCR2
Wait ( ) µs
5
*
NO
End of erasing of
all erase blocks?
YES
Clear SWE bit in FLMCR1
End of erasing
and N are listed in section 29.2.7, Flash Memory Characteristics.
2
*
4
*
2
*
Start of erase
2
*
Halt erase
2
*
2
*
2
*
2
*
3
*
Clear EV bit in FLMCR1 or FLMCR2
Wait ( ) µs
2
*
n N?
YES
Clear SWE bit in FLMCR1
Erase failure
Rev. 2.0, 11/00, page 199 of 1037
n n+1
2
*
2
*
NO