Renesas Hitachi H8S/2194 Series Hardware Manual page 559

16-bit single-chip microcomputer
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Bit 5: Master/Slave Select (MST)
Bit 4: Transmit/Receive Select (TRS)
MST selects whether the I
TRS selects whether the I
In master mode with the I
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according
to the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
Bit 5
Bit 4
MST
TRS
0
0
1
1
0
1
Bit 5
MST
Description
0
Slave mode
[Clearing conditions]
(1) When 0 is written by software
(2) When bus arbitration is lost after transmission is started in I
mode
1
Master mode
[Setting conditions]
(1) When 1 is written by software (in cases other than clearing condition 2)
(2) When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)
Rev. 2.0, 11/00, page 532 of 1037
2
C bus interface operates in master mode or slave mode.
2
C bus interface operates in transmit mode or receive mode.
2
C bus format, when arbitration is lost, MST and TRS are both reset by
Description
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
(Initial value)
(Initial value)
2
C bus format master

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