Renesas Hitachi H8S/2194 Series Hardware Manual page 364

Bit 7: Selection of the Capture Signals of the TMRU-2 (LAT)
In combination with the CPS bit (Bit 0) of the TMRM1, this bit works to select the capture
signals of the TMRU-2.
TMRM2 TMRM1
Bit 7 Bit 0
LAT CPS
0 *
1 0
1
Note: Don't care.
*
Bits 6 and 5: Selecting the Clock Source for the TMRU-1 (PS11 and PS10)
These bits work to select the inputting clock to the TMRU-1.
Bit 6 Bit 5
PS11 PS10
0 0
1
1 0
1
Bits 4 and 3: Selecting the Clock Source for the TMRU-3 (PS31 and PS30)
These bits work to select the inputting clock to the TMRU-3.
Bit 4 Bit 3
PS31 PS30
0 0
1
1 0
1
Description
Captures when the TMRU-3 underflows
Captures at the rising edge of the CFS
Captures at the edge of the IRQ3
Description
Counting at the rising edge of the CFG
Counting by the PSS, φ/4
Counting by the PSS, φ/256
Counting by the PSS, φ/512
Description
Counting at the rising edge of the DVCTL from the dividing circuit.
Counting by the PSS, φ/4096
Counting by the PSS, φ/2048
Counting by the PSS, φ/1024
(Initial value)
(Initial value)
(Initial value)
Rev. 2.0, 11/00, page 337 of 1037