Hsw (Head-Switch) Timing Generator; Overview; Block Diagram - Renesas Hitachi H8S/2194 Series Hardware Manual

28.4

HSW (Head-switch) Timing Generator

28.4.1

Overview

The HSW timing generator consists of one 5-bit counter and one 16-bit counter, matching
circuit, and two 31-bit 10-stage FIFOs.
The 5-bit counter counts the DFG pulses following a DPG pulse. Each of them determines the
timing to reset the 16-bit timer for each field. The matching circuit compares the timing data in
the most significant 16 bits of FIFO with the 16-bit timer, and controls the output of pattern data
set in the least significant 15 bits of FIFO. The 16-bit timer is a timer clocked by a φ s/4 clock
source, and can be used as a PPG (Programmable Pattern Generator) as well as a free-running
counter (FRC). If used as a free-running counter, it is cleared by overflow (FRCOVF) of the
Prescaler unit. Accordingly, two free-running counter operate in sync.
28.4.2

Block Diagram

Figure 28.22 shows a block diagram of the HSW timing generator.
Rev. 2.0, 11/00, page 650 of 1037