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28.8.4
Register Descriptions
(1) CFG Speed Preset Data Register (CFPR)
15
Bit :
Initial value :
0
R/W :
W
The 16-bit preset data that defines the specified CFG speed is set in CFPR. The preset data is
referenced to H'8000*, and can be calculated from the following equation.
CFG speed preset data =H'8000 − (
φs:
DVCFG frequency: In Hz
The constant 2 is the preset interval (see figure 28.33).
φs/n:
CFPR is a 16-bit write-only register. CFPR is accessible by word access only. Byte access
gives unassured results. No read is valid. If a read is attempted, an undetermined value is read
out. CFPR is initialized to H'0000 by a reset, stand-by or module stop.
Note: * The preset data value is calculated so that the counter will reach H'8000 when the
error is zero. When the counter value is latched as error data in the CFG speed error
data register (CFER), however, it is converted to a value referenced to H'0000.
Rev. 2.0, 11/00, page 704 of 1037
14
13
12
11
10
0
0
0
0
0
W
W
W
W
W
DVCFG frequency
Servo clock frequency in Hz (f
Clock source of the selected counter
9
8
7
6
0
0
0
0
W
W
W
W
φs/n
− 2)
/2)
OSC
5
4
3
2
1
0
0
0
0
0
W
W
W
W
W
0
0
W
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