Register Descriptions; Standby Control Register (Sbycr) - Renesas Hitachi H8S/2194 Series Hardware Manual

10.2

Register Descriptions

10.2.1

Standby Control Register (SBYCR)

Bit : 7
SSBY
Initial value : 0
R/W : R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
Only bits 0 and 1 are described here. For a description of the other bits, see section 4.2.1,
Standby Register (SBYCR). SBYCR is initialized to H'00 by a reset.
Bits 1 and 0: System Clock Select 1 and 0 (SCK1, SCK0)
These bits select the bus master clock for high-speed mode and medium-speed mode.
Bit 1 Bit 0
SCK1 SCK0
0 0
1
1 0
1
Rev. 2.0, 11/00, page 224 of 1037
6 5
STS2 STS1 STS0
0 0
R/W R/W R/W
Description
Bus master is in high-speed mode
Medium-speed clock is φ/16
Medium-speed clock is φ/32
Medium-speed clock is φ/64
4 3 2
— —
0 0 0
— —
1 0
SCK1 SCK0
0 0
R/W R/W
(Initial value)