Section 14 Timer J; Overview; Features; Block Diagram - Renesas Hitachi H8S/2194 Series Hardware Manual

14.1

Overview

The Timer J consists of twin 8-bit counters. It carries seven different operation modes such as
reloading and event counting.
14.1.1

Features

The Timer J consists of twin 8-bit reloading timers and it is usable under the various functions as
follows:
(a) Twin 8-bit reloading timers (Among the two, one is capable to make timer outputs)
(b) Twin 8-bit event counters (Capable to make reloading)
(c) 8-bit event counter (Capable to make reloading) + 8-bit reload timer
(d) 16-bit event counter (Capable to make 16-bit reloading)
(e) 16-bit reload timer (Capable to make 16-bit reloading)
(f) Remote controlled transmissions
(g) "Take up/Supply reel pulse" dividing (8 bit × 2 units)
14.1.2

Block Diagram

Figure 14.1 is a block diagram of the Timer J. The Timer J consists of two reload timers
namely, TMJ-1 and TMJ-2.

Section 14 Timer J

Rev. 2.0, 11/00, page 303 of 1037