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23.2.8 Bit Rate Register (BRR1) ................................................................................ 457
23.2.9 Serial Interface Mode Register (SCMR1) ......................................................... 464
23.2.10 Module Stop Control Register (MSTPCR) ....................................................... 465
23.3 Operation..................................................................................................................... 466
23.3.1 Overview......................................................................................................... 466
23.3.2 Operation in Asynchronous Mode.................................................................... 468
23.3.3 Multiprocessor Communication Function......................................................... 478
23.3.4 Operation in Clock Synchronous Mode ............................................................ 486
23.4 SCI1 Interrupts ............................................................................................................ 494
23.5 Usage Notes................................................................................................................. 495
Section 24 Serial Communication Interface 2 (SCI2) ..................................... 499
24.1 Overview ..................................................................................................................... 499
24.1.1 Features........................................................................................................... 499
24.1.2 Block Diagram ................................................................................................ 500
24.1.3 Pin Configuration ............................................................................................ 501
24.1.4 Register Configuration..................................................................................... 501
24.2 Register Descriptions ................................................................................................... 502
24.2.1 Starting Address Register (STAR) ................................................................... 502
24.2.2 Ending Address Register (EDAR).................................................................... 502
24.2.3 Serial Control Register 2 (SCR2) ..................................................................... 503
24.2.4 Serial Control Status Register 2 (SCSR2)......................................................... 504
24.2.5 Module Stop Control Register (MSTPCR) ....................................................... 507
24.3 Operation..................................................................................................................... 508
24.3.1 Clock .............................................................................................................. 508
24.3.2 Data Transfer Format....................................................................................... 508
24.3.3 Data Transfer Operations ................................................................................. 511
24.4 Interrupt Sources.......................................................................................................... 515
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25.1 Overview ..................................................................................................................... 517
25.1.1 Features........................................................................................................... 517
25.1.2 Block Diagram ................................................................................................ 518
25.1.3 Pin Configuration ............................................................................................ 519
25.1.4 Register Configuration..................................................................................... 520
25.2 Register Descriptions ................................................................................................... 521
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25.2.1 I
C Bus Data Register (ICDR).......................................................................... 521
25.2.2 Slave Address Register (SAR) ......................................................................... 524
25.2.3 Second Slave Address Register (SARX) .......................................................... 526
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25.2.4 I
C Bus Mode Register (ICMR) ....................................................................... 527
2
25.2.5 I
C Bus Control Register (ICCR) ..................................................................... 531
2
25.2.6 I
C Bus Status Register (ICSR) ........................................................................ 538
25.2.7 Serial/Timer Control Register (STCR) ............................................................. 543
Rev. 2.0, 11/00, page xiii of xviii
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