Renesas Hitachi H8S/2194 Series Hardware Manual page 659

(2) Reference Period Register 1 (RFD)
Bit :
15
REF15
Initial value : 1
R/W :
W
The reference period register 1 (RFD) is a buffer register which generates the reference signals
for playback (REF30), VD compensation for recording and the reference signals for free-
running. It is a 16-bit write-only register accessible by a word only. If a read is attempted, an
undetermined value is read out.
The value set in RFD should be 1/2 of the desired reference signal period. Care is required when
VD is unstable, such as when the field is weak (Synchronization with VD cannot be acquired if a
value less than 1/2 is set when in REC). When data is written in RFD, it is stored in the buffer
once, and then fetched into RFD by a match signal of the comparator. (The data which
generates the reference signal is updated from time to time by the match signal.) An enforced
write, such as initial setting, etc., should be done by a dummy read of RFD.
If a byte-write in RFD is attempted, no operation is assured. RFD is initialized to H'FFFF by a
reset, stand-by, or module stop.
Use bit 7 (ASM) and bit 6 (REC/PB) in the CTL mode register (CTLM) in the CTL circuit to
switch between record and playback modes. Use bit 4 (CR/RF bit) in the capstan phase error
detection control register (CPGCR) to switch between REF30 and CREF for capstan phase
control.
Rev. 2.0, 11/00, page 632 of 1037
14 13 12 11 10
REF14 REF13 REF12 REF11 REF10
1 1 1 1 1
W W W W W
9 8 7 6 5
REF9 REF8 REF7 REF6 REF5
1 1 1 1 1
W W W W W
4 3 2 1 0
REF4 REF3 REF2 REF1 REF0
1 1 1 1 1
W W W W W