Table of Contents
Advertisement
H'D02A: Digital Filter Control Register
Bit :
7
Initial value :
1
R/W :
H'D030: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector
H'D031: Specified DFG Speed Preset Data Register DFPR: Drum Error Detector
Bit :
15
14
Initial value :
0
0
R/W :
W
W
H'D032: DFG Speed Error Data Register DFER: Drum Error Detector
H'D033: DFG Speed Error Data Register DFER: Drum Error Detector
15
14
Bit :
Initial value :
0
0
R * /W
R * /W
R/W :
6
5
4
PTON
CP/DP
1
0
0
R/W
R/W
Capstan phase system error data transfer bit
PWM output select bit
0 Output drum phase system computation result (CAPPWM)
1 Output capstan phase system computation result (DRMPWM)
Phase system computation result PWM output bit
0 Output normal filter computation result to PWM pin.
1 Output only phase system computation result to PWM pin.
13
12
11
10
0
0
0
0
W
W
W
W
13
12
11
10
9
0
0
0
0
0
R * /W
R * /W
R * /W
R * /W
R * /W
DFUCR: Digital Filter
3
2
CFEPS
DFEPS
CFESS
0
0
R/W
R/W
Capstan speed system error data transfer bit
0 Transfer data by DVCFG signal latch.
1 Transfer data at the time of error data write.
Drum phase system error data transfer bit
0 Transfer data by HSW (NHSW) signal latch.
1 Transfer data at the time of error data write.
0 Transfer data by DVCFG2 signal latch.
1 Transfer data at the time of error data write.
9
8
7
6
5
0
0
0
0
0
W
W
W
W
W
8
7
6
5
0
0
0
0
R * /W
R * /W
R * /W
R * /W R * /W
Rev. 2.0, 11/00, page 923 of 1037
1
0
DFESS
0
0
R/W
R/W
Drum speed system error data transfer bit
0 Transfer data by NCDFG signal latch.
1 Transfer data at the time of error data
write.
4
3
2
1
0
0
0
0
W
W
W
W
4
3
2
1
0
0
0
0
0
0
R * /W R * /W
R * /W R * /W
0
0
W
Advertisement
Table of Contents
