Renesas Hitachi H8S/2194 Series Hardware Manual page 520

16-bit single-chip microcomputer
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Read TDRE flag in SSR1
No
Write transmit data to TDR1 and
clear TDRE flag in SSR1 to 0
Read ORER flag in SSR1
Read RDRF flag in SSR1
No
Read receive data in RDR1, and
clear RDRF flag in SSR1 to 0
No
All data received?
Clear TE and RE
bits in SCR1 to 0
Note: When switching from transmit or receive operation
to simultaneous transmit and receive operations, first clear
the TE bit and RE bit to 0, then set both these bits to 1
simultaneously.
Figure 23.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
Initialization
[1]
Start transfer
[2]
TDRE=1
Yes
Yes
ORER=1
Error handling
No
[4]
RDR=1
Yes
[5]
Yes
< End >
SCI1 initialization:
[1]
The SO1 pin is designated as the transmit
data output pin, and the SI1 pin is
designated as the receive data input pin,
enabling simultaneous transmit and receive
operations.
SCI1 status check and transmit data write:
[2]
Read SSR1 and check that the TDRE flag
is set to 1, then write transmit data to TDR1
and clear the TDRE flag to 0.
Transition of the TDRE flag from 0 to 1 can
also be identified by a TXI interrupt.
Receive error handling:
[3]
If a receive error occurs, read the ORER
flag in SSR1, and after performing the
appropriate error handling, clear the ORER
[3]
flag to 0. Transmission/reception cannot
be resumed if the ORER flag is set to 1.
SCI1 status check and receive data read:
[4]
Read SSR1 and check that the RDRF flag
is set to 1, then read the receive data in
RDR1 and clear the RDRF flag to 0.
Transition of the RDRF flag from 0 to 1 can
also be identified by an RXI interrupt.
Serial transmission/reception continuation
[5]
procedure:
To continue serial transmission/reception,
before the MSB (bit 7) of the current frame
is received, finish reading the RDRF flag,
reading RDR1, and clearing the RDRF flag
to 0. Also before the MSB (bit 7) of the
current frame is transmitted, read 1 from
the TDRE flag to confirm that writing is
possible, then write data to TDR1 and clear
the TDRE flag to 0.
Rev. 2.0, 11/00, page 493 of 1037

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