Renesas Hitachi H8S/2194 Series Hardware Manual page 481

Bit 7: Transmit Data Register Empty (TDRE)
Indicates that data has been transferred from TDR1 to TSR and the next serial data can be
written to TDR1.
Bit 7
TDRE Description
0 [Clearing conditions]
When 0 is written in TDRE after reading TDRE = 1
1 [Setting conditions]
(1) When the TE bit in SCR1 is 0
(2) When data is transferred from TDR1 to TSR and data can be written to TDR1
Bit 6: Receive Data Register Full (RDRF)
Indicates that the received data is stored in RDR1.
Bit 6
RDRF Description
0 [Clearing conditions]
When 0 is written in RDRF after reading RDRF = 1
1 [Setting conditions]
When serial reception ends normally and receive data is transferred from RSR to
RDR1
Note: RDR1 and the RDRF flag are not affected and retain their previous values when an error
is detected during reception or when the RE bit in SCR1 is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Rev. 2.0, 11/00, page 454 of 1037
(Initial value)
(Initial value)