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SDA
SCL
1-7
S
SLA
2
Table 25.4 I
C Bus Data Format Symbols
S
Start condition. The master device drives SDA from high to low while SCL is hig
SLA
Slave address, by which the master device selects a slave device
:
R/
Indicates the direction of data transfer: from the slave device to the master device
when R/
A
Acknowledge. The receiving device (the slave in master transmit mode, or the
master in master receive mode) drives SDA low to acknowledge a transfer
DATA
Transferred data. The bit length is set by bits BC2 to BC0 in ICMR. The MSB-
first or LSB-first format is selected by bit MLS in ICMR
P
Stop condition. The master device drives SDA from low to high while SCL is high
25.3.2
Master Transmit Operation
2
In I
C bus format master transmit mode, the master device outputs the transmit clock and
transmit data, and the slave device returns an acknowledge signal. The transmission procedure
and operations synchronize with the ICDR writing are described below.
[1] Set bit ICE in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit IICX
in STCR, according to the operating mode.
[2] Read the BBSY flag in ICCR to confirm that the bus is free.
[3] Set bits MST and TRS to 1 in ICCR to select master transmit mode.
[4] Write 1 to BBSY and 0 to SCP. This changes SDA from high to low when SCL is high, and
generates the start condition.
[5] Then IRIC and IRTR flags are set to 1. If the IEIC bit in ICCR has been set to 1, an interrupt
request is sent to the CPU.
[6] Write the data (slave address + R/
issued and the start conditon has been generated, write data to ICDR. If this procedure is not
followed, data may not be output correctly. With the I
or the FSX bit in SARX is 0), the first frame data following the start condition indicates the
7-bit slave address and transmit/receive direction. As indicating the end of the transfer, and
so the IRIC flag is cleared to 0. After writing ICDR, clear IRIC immediately not to execute
other interrupt handling routine. If one frame of data has been transmitted before the IRIC
8
9
1-7
R/W
A
DATA
Figure 25.5 I
:
is 1, or from the master device to the slave device when R/
:
) to ICDR. After the start condition instruction has been
8
9
1-7
A
2
C Bus Timing
2
C bus format (when the FS bit in SAR
Rev. 2.0, 11/00, page 547 of 1037
8
9
DATA
A/A
:
is 0
P
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