Renesas Hitachi H8S/2194 Series Hardware Manual page 568

Bit 4: Second Slave Address Recognition Flag (AASX)
2
In I C bus format slave receive mode, this flag is set to 1 if the first frame following a start
condition matches bits SVAX6 to SVAX0 in SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX Description
0 Second slave address not recognized
[Clearing condition]
(1) When 0 is written in AASX after reading AASX = 1
(2) When a start condition is detected
(3) In master mode
1 Second slave address recognized
[Setting condition]
• When the second slave address is detected in slave receive mode while FSX = 0
Bit 3: Arbitration Lost (AL)
This flag indicates that arbitration was lost in master mode. The I
bus. When two or more master devices attempt to seize the bus at nearly the same time, if the
2
I C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the
bus has been taken by another master.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL Description
0 Bus arbitration won (Initial value)
[Clearing conditions]
(1) When ICDR data is written (transmit mode) or read (receive mode)
(2) When 0 is written in AL after reading AL = 1
1 Arbitration lost
[Setting conditions]
(1) If the internal SDA and SDA pin disagree at the rise of SCL in master transmit
mode
(2) If the internal SCL line is high at the fall of SCL in master transmit mode
(Initial value)
2
C bus interface monitors the
Rev. 2.0, 11/00, page 541 of 1037