Renesas Hitachi H8S/2194 Series Hardware Manual page 949

H'D029: Capstan System Digital Filter Control Register CFIC: Digital Filter
Bit : 7
1
Initial value :
R/W :
Capstan system range over flag
0
1
Note: * Only 0 can be written.
Rev. 2.0, 11/00, page 922 of 1037
6 5
CROV CPHA CZPON
0 0
R/(W) *
R/(W) R/W
Capstan phase system Z
0 Phase system Z
1 Phase system Z
Capstan phase system filter computation start bit
0 Phase system filter computation is OFF.
Phase system computation result Y is not added to Es.
1 Phase system filter computation is ON.
Filter computation result does not exceed 12 bits.
Filter computation result exceeds 12 bits.
4 3 2
CZSON CSG2
0 0 0
R/W R/W
Capstan system gain control bit
CSG2 CSG1 CSG0
0 0
1
1 0
1
-1
Capstan speed system Z
-1
0 Speed system Z reflects CZs value.
-1
1 Speed system Z does not relect CZs value.
-1
initialization bit
-1
reflects CZp value.
-1
does not relect CZp value.
1 0
CSG1 CSG0
0 0
R/W R/W
Description
0 x 1
1 x 2
0 x 4
1 x 8
0 x 16
1 (x 32) *
0 (x 64) *
1 Invalid (do not set)
initialization bit