Flash Memory Control Register 2 (Flmcr2) - Renesas Hitachi H8S/2194 Series Hardware Manual

7.3.2

Flash Memory Control Register 2 (FLMCR2)

Bit :
7
FLER
Initial value :
0
R/W :
R
FLMCR2 is an 8-bit register that monitors the presence or absence of flash memory
program/erase protection (error protection) and performs setup for flash memory program/erase
mode. FLMCR2 is initialized to H'00 by a reset. The ESU and PSU bits are cleared to 0 in
power-down state (excluding the medium-speed mode, module stop mode, and sleep mode),
hardware protect mode, or software protect mode.
Bit 7: Flash Memory Error (FLER)
Indicates that an error has occurred during an operation on flash memory (programming or
erasing). When FLER is set to 1, flash memory goes to the error-protection state.
Bit 7
FLER Description
0 Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition] Reset or hardware standby mode
1 An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition] See section 7.6.3, Error Protection
Bits 6 to 2: Reserved
These bits cannot be modified and are always read as 0.
Bit 1: Erase Setup (ESU)
Prepares for a transition to erase mode. Set this bit to 1 before setting the E bit to 1 in FLMCR1.
Do not set the SWE, PSU, EV, PV, E, or P bit at the same time.
Bit 1
ESU Description
0 Erase setup cleared
1 Erase setup
[Setting condition] When FWE = 1, and SWE = 1
Rev. 2.0, 11/00, page 134 of 1037
6 5 4
— — —
0 0 0
— — —
3 2 1
— — ESU
0 0 0
— — R/W
0
PSU
0
R/W
(Initial value)
(Initial value)