Renesas Hitachi H8S/2194 Series Hardware Manual page 936

Instruc-
tion H N
−
SHAL
−
SHAR
−
SHLL
−
SHLR 0
− −
SLEEP
− −
STC
− −
STM
STMAC Cannot be used in this LSI.
SUB
− −
SUBS
SUBX
−
TAS
− −
TRAPA
−
XOR
XORC
Z V C
0
0
0
− − −
− − −
− − −
− − −
−
0
− − −
−
0
Definition
N=Rm
⋅ ⋅ ⋅
Z=
RRRRRR
5P 5P 5
⋅
V=Dm⋅Dm-1+
'P 'P
V=Dm⋅Dm-1⋅Dm-2⋅
'P
(In case of 2bits)
C=Dm , C=Dm-1
(In case of 1 bit)
N=Rm
⋅ ⋅ ⋅
Z=
RRRRRR
5P 5P 5
C=D0 , C=D1
(In case of 1 bit)
N=Rm
⋅ ⋅ ⋅
Z=
RRRRRR
5P 5P 5
C=Dm , C=Dm-1
(In case of 1 bit)
N=Rm
⋅ ⋅ ⋅
Z=
RRRRRR
5P 5P 5
C=D0 , C=D1
(In case of 1 bit)
H=Sm-4⋅ +
'P 'P
N=Rm
⋅ ⋅ ⋅
Z=
RRRRRR
5P 5P 5
⋅Dm⋅
V= +Sm⋅
6P 5P 'P
⋅Rm+Sm⋅Rm
C=Sm⋅ +
'P 'P
H=Sm-4⋅ +
'P 'P
N=Rm
⋅ ⋅
Z=Z'⋅
RRRRRR
5P 5
⋅Dm⋅
V= +Sm⋅
6P 5P 'P
⋅Rm+Sm⋅Rm
C=Sm⋅ +
'P 'P
N=Dm
⋅ ⋅ ⋅
Z=
RRRRRR
'P 'P '
N=Rm
⋅ ⋅ ⋅
Z=
RRRRRR
5P 5P 5
Value in the bit corresponding to execution
result is stored. No flag change when EXR.
Rev. 2.0, 11/00, page 909 of 1037
(In case of 1 bit)
⋅ ⋅
'P 'P
(In case of 2 bits)
(In case of 2 bits)
(In case of 2 bits)
(In case of 2 bits)
⋅Rm-4+Sm-4⋅Rm-4
⋅Rm
⋅Rm-4+Sm-4⋅Rm-4
⋅Rm